As the development of computer systems proceeds, increases to the processing speed are continually desired. Typically, reduction in device geometries of system components is sought to help increase speed and density. Associated with the reduction in device size is a reduction in power supply voltage requirements. For example, it is possible for normal operating voltages in the processor to range between 0 volts (V) and 1.8 V.
Further, advances in processor technology is occurring at a much faster pace than in typical input/output (I/O) devices. Off chip drivers (OCDs) of processors interface with many different external devices, such as ASICs (application specific integrated circuits), SRAMs (static random access memories), etc. These external devices tend to be designed in earlier technologies and thus use higher core voltages, which in turn results in their driving higher voltages. For example, normal operating voltages range between 0 V and 3.3 V. The higher voltages driven by the external devices potentially damage FET (field effect transistor) devices in the output stage of the OCDs by violating the gate-source/drain voltage limitations of the processor technology.
For example, some fabrication techniques impose a relatively low predetermined limit on a maximum safe difference between a voltage level at a transistor's gate and a voltage level at a source/drain region of the transistor. In such a situation, if the transistor's source/drain region has a voltage level that differs from the voltage level at the transistor's gate by more than the predetermined limit, then the transistor's gate oxide could be damaged in a manner that destroys the transistor's operability.
The OCD design therefore has to be voltage level compatible with these existing external support devices. Usually, this results in OCDs being designed for use with a higher power supply voltage than that of the core processor logic. Additional design challenges regarding thin gate oxide protection and circuit performance thus result.
Accordingly, what is needed is improved thin gate oxide protection and circuit performance for OCDs and provision of improved design margins and device reliability.